Altera Cyclone V GT FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 51)

Chapter 2: Board Components 2–43

Memory

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

DDR3B_DQ3

AC31 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ4

AH32 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ5

Y28 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ6

AN34 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ7

Y27 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ8

AD32 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ9

AH33 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ10

AB31 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ11

AJ34 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ12

AA31 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ13

AK34 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ14

W31 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ15

AG33 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQS_P0

Y29

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 0

DDR3B_DQS_N0

Y30

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 0

DDR3B_DQS_P1

W29

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 1

DDR3B_DQS_N1

W30

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 1

DDR3B_ODT

AA32 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

Y32 1.5-V SSTL Class I Row address select

DDR3B_RESETN

AG31 1.5-V SSTL Class I Reset

DDR3B_WEN

AM34 1.5-V SSTL Class I Write enable

DDR3B_ZQ01

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U22)

DDR3B_A0

H29 1.5-V SSTL Class I Address bus

DDR3B_A1

K28 1.5-V SSTL Class I Address bus

DDR3B_A2

K34 1.5-V SSTL Class I Address bus

DDR3B_A3

L32 1.5-V SSTL Class I Address bus

DDR3B_A4

R32 1.5-V SSTL Class I Address bus

DDR3B_A5

R33 1.5-V SSTL Class I Address bus

DDR3B_A6

N32 1.5-V SSTL Class I Address bus

DDR3B_A7

G33 1.5-V SSTL Class I Address bus

DDR3B_A8

AE34 1.5-V SSTL Class I Address bus

DDR3B_A9

L27 1.5-V SSTL Class I Address bus

DDR3B_A10

V33 1.5-V SSTL Class I Address bus

DDR3B_A11

U33 1.5-V SSTL Class I Address bus

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 6)

Board Reference

Schematic

Signal Name

Cyclone V GT

Pin Number

I/O Standard Description

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 65 66

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