Altera Cyclone V E FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 41)

Chapter 2: Board Components 2–33

Memory

March 2013 Altera Corporation Cyclone V E FPGA Development Board

Reference Manual

DDR3_A11

E20 1.5-V SSTL Class I Address bus

DDR3_A12

C25 1.5-V SSTL Class I Address bus

DDR3_A13

B13 1.5-V SSTL Class I Address bus

DDR3_BA0

J18 1.5-V SSTL Class I Bank address bus

DDR3_BA1

F20 1.5-V SSTL Class I Bank address bus

DDR3_BA2

D19 1.5-V SSTL Class I Bank address bus

DDR3_CASN

L20 1.5-V SSTL Class I Row address select

DDR3_CKE

C11 1.5-V SSTL Class I Column address select

DDR3_CLK_P

J20

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3_CLK_N

H20

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3_CSN

G17 1.5-V SSTL Class I Chip select

DDR3_DM0

D23 1.5-V SSTL Class I Write mask byte lane

DDR3_DM1

D18 1.5-V SSTL Class I Write mask byte lane

DDR3_DQ0

A25 1.5-V SSTL Class I Data bus byte lane 0

DDR3_DQ1

D22 1.5-V SSTL Class I Data bus byte lane 0

DDR3_DQ2

C21 1.5-V SSTL Class I Data bus byte lane 0

DDR3_DQ3

C19 1.5-V SSTL Class I Data bus byte lane 0

DDR3_DQ4

C20 1.5-V SSTL Class I Data bus byte lane 0

DDR3_DQ5

C22 1.5-V SSTL Class I Data bus byte lane 0

DDR3_DQ6

D25 1.5-V SSTL Class I Data bus byte lane 0

DDR3_DQ7

D20 1.5-V SSTL Class I Data bus byte lane 0

DDR3_DQ8

B24 1.5-V SSTL Class I Data bus byte lane 1

DDR3_DQ9

A21 1.5-V SSTL Class I Data bus byte lane 1

DDR3_DQ10

B21 1.5-V SSTL Class I Data bus byte lane 1

DDR3_DQ11

F19 1.5-V SSTL Class I Data bus byte lane 1

DDR3_DQ12

C24 1.5-V SSTL Class I Data bus byte lane 1

DDR3_DQ13

B23 1.5-V SSTL Class I Data bus byte lane 1

DDR3_DQ14

E18 1.5-V SSTL Class I Data bus byte lane 1

DDR3_DQ15

A23 1.5-V SSTL Class I Data bus byte lane 1

DDR3_DQS_P0

K20

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

DDR3_DQS_N0

J19

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 0

DDR3_DQS_P1

L18

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 1

DDR3_DQS_N1

K18

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 1

DDR3_ODT

H19 1.5-V SSTL Class I On-die termination enable

Table 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Schematic

Signal Name

Cyclone V E FPGA

Pin Number

I/O Standard Description

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 55 56

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