Altera Cyclone III LS FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 4)

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

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Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

1 2 3 4 5 6 7 8 9 ... 57 58

Reference Manual 1
MNL-01049-1.0 2
Contents 3
Additional Information 4
1. Overview 5
Board Component Blocks 6
Chapter 1: Overview 1–3 7
Handling the Board 8
2. Board Components 9
Board Overview 10
I/O Resources 13
Note to Table 2–4: 14
II CPLD EPM2210 System 15
II device (U22) 15
Table 2–6 lists the MAX 18
Configuration 19
Figure 2–4. JTAG Chain 20
Status Elements 24
Note to Table 2–8: 24
Setup Elements 25
Note to Table 2–11: 26
Clock Circuitry 28
Bank 6Bank 5 29
Note to Table 2–20: 30
General User Input/Output 31
User-Defined DIP Switches 32
User-Defined LEDs 33
10/100/1000 Ethernet 35
Components and Interfaces 36
High-Speed Mezzanine Cards 37
Note to Table 2–34: 40
Note to Table 2–35: 43
Power Distribution System 52
Power Measurement 53
Power Supply 54
Notes to Table 2–48: 55
Note to Table: 57
Typographic Conventions 58

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